1. Field of the Invention
The present invention relates to data processing apparatus, and in particular to data processing circuits that have one or more power saving modes of operation.
2. Description of the Prior Art
There is currently much interest in reducing the power consumption of data processing circuits, such as `Application Specific Integrated Circuits` (ASICs). It is becoming more commonplace for these devices to be used in products which operate from battery power, such as portable laptop computers, mobile phones, personal organisers, etc. In such situations, it is clearly desirable to reduce the power consumption of these processing devices as much as possible, in order to improve the battery life of the products, i.e. the amount of time the products can be used for before needing to replace or recharge the batteries. However, it is not just in the area of battery powered products where power consumption is a concern, and there is generally a desire to reduce power consumption wherever possible.
To reduce the problems of power consumption, it is known to provide one or more power saving modes of operation into which the product may be placed in order to conserve battery power. As process technology improves, increasing levels of system functionality are being integrated into a single chip, with a corresponding increase in the number and complexity of such power saving modes. These are designed to allow the maximum system flexibility while aiming to reduce the average power consumption of the system.
Data processing circuits used in products of the above type typically contain a number of clocked circuit elements, which are supplied with a common clock signal by a clock bus. In a circuit where the reduction of power consumption is a key requirement, software or hardware controlled power saving modes have been developed to reduce the average power consumption.
With the known techniques, power consumption in each of the power saving modes is typically reduced by disabling circuit elements which are not in use by gating out the clock input at the circuit element. However, using this technique, the power dissipated in the main clock bus itself, due to the high capacitance being driven, will still be significant in all operating modes. FIG. 1 shows an example circuit, using this prior art technique to reduce power consumption. There are three operating modes (A, B and C) of which mode A corresponds to the whole circuit being active, and B and C require different combinations of the circuit elements to be clocked.
More specifically, in Mode A, all the circuit elements 115, 120, 125, 130, 135, 140, 145, 150 and 155 are arranged to receive a clock signal over clock bus 110 from the clock source 100. Each circuit element except for circuit element 120 has an AND gate at its input, one input of the AND gate receiving the clock signal from clock bus 110, and the other input receiving an enable/disable control signal. In Mode A, the control signal for all circuit elements has logic value `1`, and hence each circuit element will be enabled to receive the clock signal from clock bus 110.
There are three control signal lines 160, 165, 170 used in the circuit illustrated in FIG. 1 to ensure that only the required circuit elements arc clocked for each of the power saving modes B and C. Hence in mode B, the control signal line 160 provides a disable signal (logic value `0`) to circuit elements 115, 125, 145 and 155, whereby those circuits are disabled by locally gating out the clock signal. Additionally, the control signal line 165 also provides a disable signal to circuit element 135, thereby disabling that circuit element. Hence, in mode B, only circuit elements 120, 130, 140 and 150 arc clocked, although the clock signal has still been provided over the clock bus to each of the circuit elements in the circuit.
Similarly, in mode C, control signal lines 160 and 170 provide a logic value `0` signal to locally disable circuit elements 115, 125, 145, 155, 130, 140 and 150, leaving only circuit elements 120 and 135 operating in mode C.
Whilst the above technique clearly provides power saving modes of operation, by locally disabling clock signals in the unused circuit elements, the percentage of the total power consumption resulting from the driving of the main clock bus will still be significant.
Many circuits, particularly those intended for incorporation into portable products, are designed with the intent that the modes of operation used for the largest proportion of time will be power saving modes. In this case, it is particularly advantageous to reduce the power consumption in those power saving modes of operation.
Further, a single-chip will often contain one or more large custom macrocells which constrain the layout of the remaining logic to be spread over a large area, with an associated increase in the total length of clock bus routing. Also, pin out constraints may result in some circuit elements being physically located far from the clock source. These factors will generally increase the power consumption of the main clock bus.
Hence, it is an object of the present invention to provide a data processing circuit which exhibits improved power savings in all operating modes.